Microprocessor power supplies are often designed to provide normal operation for short periods during primary power interruptions. The source of power during the interruption is normally a bank of storage capacitors. Over the years designers have steadily improved the holdup period so that the next generation of microprocessor power supplies, especially those used in military applications, will be required to provide normal operation for up to 50 milliseconds. The conventional method of meeting this requirement is to increase the size of the capacitor bank. For some applications, particularly power supplies for airborne computer systems, the "brute force" method (simply increasing the capacitance) is size, weight, and cost prohibitive.
Another approach is to provide holdup power only for the random access memory (RAM), i.e., the volatile memory. This approach is viable because only the information stored in RAM is permanently lost upon loss of power. Information and instructions stored in read only memory (ROM), on the other hand, is nonvolatile and is not permanently lost upon loss of power. Since RAM consumes signficantly less power than the total system, power supplies designed according to this approach can provide holdup power for longer periods. However, an undesirable side-effect of such designs is the nontransparent operation of the computer during the power interruption and the system power "turn-on" and "turn-off" sequencing requirements.
Therefore, a power holdup circuit that provides transparency to primary power interruptions with a minimum of capacitance and maximum efficiency is needed.